GEKCO Model VG10
Test Pattern Generator
THEORY OF OPERATION
Video Pattern Generation
Pixel Input Bus
On Screen Display Bus
Output Filter Networks
MEMORY CONTROL LOGIC
Memory Address Control
Static Ram Memory
Front Panel Interface
Serial Bus Communication
On Screen Display
The GEKCO video pattern generator is a versatile instrument for testing a wide range of video processing and display applications. Please refer to the companion document, A Video Tutorial, which describes in detail, a review of color video and why do we need a video test pattern generator and what each test pattern is used for . This unit generates many of the major video test patterns needed for video system evaluation and test.
Figure 1. Front Panel
Video Pattern Selection
Front Panel Control
The Front Panel allows selection of the desired test pattern and on screen display control. Pattern Selection The (up) and ¯ (down) buttons are used to control the pattern selection. If the enhanced patterns are available the left and right buttons are used to page to the next page of patterns. Press the (up) arrow button to select patterns in sequential order or down to reverse the selection ordering. Patterns will change while the switch is pressed or step through them one at a time for each key press. Un press the switch to halt the pattern sequencing. If no changes were made after 4 seconds the current pattern setup will be stored to non-volatile memory for later recall on power up.
On Screen Display (OSD) Control
The arrow buttons, up, down, left and right are used to setup the OSD. The “Enter” button is used in a dual purpose mode depending on the time that it is held pressed. A short press turns on or off the OSD character display. A long press, about 2 seconds will start the OSD selection mode.
Use the up, down, left and right control buttons to chose the appropriate character. The control button can be held down to sequence the move at a 1 character per second rate. Push the “Enter” button to select the character. The selected character will be shown on the display line where the box was blinking and the blinking box will move to the next position waiting for the selection of another character. The display line can be created in this manner up to 12 characters. To backspace select the left arrow icon on the menu and to add a space select the right arrow icon.
The background and color of the characters in text message is adjustable. The background can either be a black block outline or a black shadow outline. Move the selection cursor to any characters on the menu that spell “BKGRND”. Push the “Enter” button to toggle the background mode.
The character color can be selected in a similar manor. Select any characters on the menu that spell “COLOR”. Push the “Enter” button to sequence through the colors. The colors available are, Gray, Magenta, Cyan, Blue, Yellow, Red, Green and Black. The colors will sequence through the list and repeat.
To exit any selection mode move the blinking cursor to the word “END” and press Enter.
This will display and allow movement of the text message. Use the arrow keys to position the display as desired. Press Enter again to exit the OSD menu and return to normal operation.
All the OSD parameters are stored to non-volatile memory for recall on power up.
The OSD Display can be turned On or Off. If it is not desired press Enter until the text display disappears and then it can be turned on again after a 2 second wait by pressing Enter again until the display re-appears.
The Configuration Control dip switch is used to configure the unit for NTSC or PAL format video and to enable the test diagnostics on power up. Not implementated at this time. Future versions will support PAL format.
This unit uses digital signal processing so there is little need for adjustment. The only adjustments that may be required are Output Video and Audio level adjusments.
Calibration Output Video Level Adjustment
Terminate the composite video output into a 75 ohm load and measure the video output level using the SMPTE bar pattern. Adjust R35 for a 1V p-p output level.
Output Audio Level Adjustment
Terminate the audio output into a 600 ohm load and adjust R25 for 0 dBu (.775 VAC rms) output level.
Theory of Operation
The video pattern generator creates the composite video waveforms, described in the companion document, A Video Tutorial, with the following functional blocks.
The functional blocks are from back to front, Video Encoder, SRAM Pattern Memory, Eprom Pattern Memory, On Screen Display, Memory Control, and the Microcontroller. Let’s start from the back end and work forward in our detail discussion of how this unit works.
The Composite Video and S-VHS outputs are generated by the Video Encoder. The Video Encoder generates the analog video from digital data from one of two input ports. The two ports are called Pixel Data and On Screen Display data or OSD for short. These two data streams come from the Pattern Memory. The Pattern Memory stores the digital information to create the waveform and presents the data to the Encoder. This design has two sources of Pattern Memory, Static Random Access Memory (SRAM) and Electrically Programmable Read Only (EPROM) Memory. The Memory control and Microcontroller use the sync signal from the Encoder for timing information and control the Pattern Memory to provide the digital data to the Video Encoder at the proper time.
The Video Encoder has a number of built in functions, a sync generator, digital signal processing and the digital to analog conversion to create the composite video waveform. The sync signals are created in the encoder and the video waveforms can come into two ports, a pixel data port and a on screen display (OSD) port. One bit on the OSD port determines which port is used and can be dynamically switched. The encoder block adds sync information to the selected input port data and creates the composite video waveform. The combined digital signal is converted to analog and adjustable on the output. Since the encoder generates the sync signals it is the master timing source for the pattern generator.
The Encoder is programmed to generate Vertical and Horizontal Sync, and Composite Blanking for the Microcontroller, Memory Control functions and On Screen Display. A IIC bus is used to program the encoder by the Microcontroller.
Digital to Analog Conversion
The Encoder has three D to A converters. One for the Composite Video, Luminance (Y) and Chrominance (C). The digital input data is 2 times over sampled and converted to analog at a clock rate of 27 MHz.
Output Video Filtering
Since the video encoder generates analog signals from a digital source the analog output contains digital samples or discrete steps. The analog filters on the output smooth out the discrete steps.
The micro controller’s function is to initialize the peripherals, load the static ram display memory, and actively control the line pattern to create the test pattern.
The microcontroller has the following jobs:
1. Dynamically select the proper video pattern line to display
2. Create the video line pattern and store in static ram memory.
3. Monitor the front panel switches for pattern control and OSD creation and control.
4. Initialize and program the video encoder
5. Initialize the On Screen Display Front Panel Interface
The Front Panel switches are read by the microcontroller on the data bus by a bus transceiver. The switches allow pattern selection and On Screen Display control. The Configuration Dip Switch allows for video format selection and test diagnostics enable. The video format can either be NTSC or PAL. If the test bit is selected on the dip switch the internal diagnostics test is ran during initialization. Normally this should be off to reduce the start up time.
Memory and OSD Control
The Memory and OSD Control block perform the pixel memory address generation , pixel clock division and OSD data control.
Video Pattern Generation
There are two sources of the pattern image. One for the OSD port and one for the pixel port. The video encoder either converts the OSD port or the pixel data port to analog video with sync.
The On Screen Display (OSD) port memory is a smaller memory for less complicated patterns.
Pixel Port Memory
The pixel port memory is used for the more complicated higher resolution video patterns. The pixel data rate is twice the rate of the OSD port and the data width is much greater so it takes more memory.
The On Screen Display (OSD) is a stand alone character generator. The OSD receives synchronizing information from the Encoder and generates the video pattern and the proper timing to display previously created character text strings.
The audio source is created by a wein bridge 1 kHz oscillator. A dual op amp driver is used for balanced audio output.
Power Supply Power to the unit is available through a external AC to DC plug in transformer. 9 to 12 VDC is required at the power connector. A internal regulator powers the main circuitry and the audio section has a negative supply provided by a simple switching supply circuit.
The Brooktree BT866 Composite Video Encoder, U14, is used to generate analog composite video and Y/C (S-Video) from a digital 16 bit data stream or a 4 bit OSD input. The BT866 also generates the sync timing signals necessary for the composite video and control sections of the design. For more detailed information on the encoder refer to the BT866 data sheet from Brooktree.
Pixel Input Bus
The pixel digital data is 24 bits wide. 8 bits are for luminance and 8 bits each of color difference data. The enhanced pattern memory data is connected to this bus.
On Screen Display Bus
The OSD port input is the 4 bit address for a look up table to create a 24 bit digital value. This look up table is initialized on power up and is used for the less complicated patterns in this design and the On Screen Display.
There are three analog outputs. One for composites video and two for S-VHS video. The luminance Y channel and chrominance C channel. Output Filter Networks A three-pole elliptic filter (1 inductor, 3 capacitors) with a 6.75MHz passband is used to provide at least 45 dB attenuation (including sinx/x loss) of frequency components above 20 MHz. There is one filter network for each analog output, composite video and the S-video luminance Y and chrominance C channel.
Memory Control Logic
The control logic used in the design is implemented with Lattice in circuit programmable logic. The logic is separated into two functions. One is Address Control and every thing else is titled Miscellaneous Control. Each logic block is implemented in a Lattice 2032 Electrically Erasable Programmable Logic Device (EEPLD).
Memory Address Control
The Address Controller allows the micro controller to control the address bus during power up initialization and then during normal mode the address bits are a counter of the pixel clock. Bits 0 through 8 are outputs of a pixel counter and the high order bits 9 to 14 are controlled by the micro controller to select which line pattern is displayed during that line.
The Miscellaneous Control block has the following functions. A fixed pixel counter pre-scalar, a mux to allow control logic to be selected during initialization and the demultiplexer to separate the 8 bit byte to two 4 bit nibbles with another mux to select either OSD data or pixel display pattern data.
Static Ram Memory
The pattern memory, U9, is a 8k by 8 Static Ram for the standard option and 32k by 8 Static Ram for the multiple pattern option. The memory is organized as 16 or 64 lines of 512 pixels by 4 bits per pixel. During the initialization sequence the pixel patterns stored in the micro controller are transferred to the static ram. Once initialization is complete the address control logic controls the address bus to generate the pixel pattern necessary for the specific display pattern.
The Pattern Eproms, U7 and U8, are used to generate special patterns needed for extra test functions. The memory is organized as two banks of 32k x 8. One bank is used for the Luminance, U7 and one for the Chrominance channel, U8. Each memory bank has 32 lines of 1024 pixels. Only 720 pixels per line are used in this design.
The Bus Transceiver, U2, is used to allow the micro controller to take over the pixel bus and read and write data to the static ram. The address decoder is used to control the enable and bus direction on the transceiver.
The microcontroller, U1, is a Motorola MC68HC705P9 multipurpose controller. The clock is divided by 8 from the 27 MHz system oscillator by U12, and enters the part on pin 27. The reset signal on pin1 is active low and controlled by U4. Multipurpose I/O PA0-PA7 are used for peripheral chip selects and memory control. PB5-7 are used for Serial Buss Communication and the IIC buss to communicate with the peripheral devices. PC0-7 are used for the data buss to load and read from SRAM memory. See the port assignments map for details.
The address decoder U5, a GAL16V8, decodes the address bits to create peripheral chip selects to enable different devices on the data bus. See the memory map in the software section for the address decoding map.
Front Panel Interface
The Bus Transceiver U3, a 74HC245, is used to allow the micro controller to read the front panel switches and the configuration dip switch. When the microcontroller desires to read the switches, pin 19 is asserted low and the switch data is placed on the data buss.
Front Panel Switches
The Front Panel Switches, SW1- SW4 are placed on data bits D0-D4 when the buss transceiver is enabled. Configuration Dip Switch Data bits D6 and D7 correspond to video format selection and test diagnostics enable.
The Non-volatile Memory, U6, a 93C46 Serial EEPROM, is used to store pattern selection and On Screen Display characters and position while power is removed from the generator. The Serial Bus is used to communicate to the EEPROM.
The microprocessor supervisor, U4, is a Maxim MAX699. This device asserts reset low if the supply voltage falls below 4.4 V. Once the supply recovers to above 4.65 volts reset is deasserted after 140 ms.
Serial Bus Communication
The Serial Bus allows the microcontroller to communicate with the OSD and the Serial EEPROM. This is accomplished with the PB port of the microcontroller. IIC Communication The (IIC) Bus is used to communicate with the Video Encoder. The same pins on the microcontroller are used for the IIC bus as with the serial bus.
On Screen Display
The On Screen Display (OSD),U11, is accomplished using a NEC uPD6453 On Screen Display IC. The timing control signals from the encoder are needed as well as the display clock, a derived clock, from the misc control EPLD, U12. For detail operation of the NEC OSD see the uPD6453 data sheet from NEC.
The Audio Oscillator is a classic Wein bridge design with components selected for a frequency of 1kHz. The Wein bridge consists of an RC series network, R19 and C27, and an RC parallel network of R18 and C29. One half of U13 is the oscillator op amp and the other half is used as a peak detector to set the gain of the feed back stage with Q1. U17 is the output driver designed to drive a 600 ohm load with 0 dBu of audio. The output level is adjusted with R25 in the feed back path of one half of U17.
The power supply consists of a external 120 VAC to 9 VDC plug in transformer, TI, connected to power connector PS1. The main logic components are powered by +5V. D8 is a reverse current protection diode and provides some voltage drop to the linear regulator VR1. VR1 is a standard LM340 5 volt regulator. The negative supply for the audio section is generated by the Maxim switching regulator, U16, a MAX635.
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